It is the practice today to mount many integrated circuit chips on a common substrate, which substrate interconnects to the chips via input/output contact lands. Such common substrates include multiple layers of ceramic sheets having printed wiring and thousands of vias which selectively interconnect the printed wiring in the various layers. It frequently becomes necessary to modify the internal circuitry within such substrates to correct for defective lines and/or vias and to make changes in the circuitry to accommodate design alterations to the semiconductor chips.
A number of techniques are present in the prior art for accomplishing engineering changes to chip/module package arrangements. In U.S. Pat. No. 4,489,364 to Chance et al., a chip carrying module is described that includes engineering change lines buried in the module. Those engineering change lines are interrupted periodically and connect to a set of vias extending to the upper surface of the module between chips mounted thereon. There, the vias are interconnected by dumbbell-shaped pads which include a narrow link. By subsequent laser deletion of the link, circuit lines can be disconnected and other dumbbell-shaped pads can be interconnected by means of additive wiring.
Another technique for making engineering changes involves the use of an interposer module between a semiconductor chip and an underlying ceramic substrate. In U.S. Pat. No. 4,202,007 to Dougherty et al., an interposer module is shown which supports a semiconductor chip having bump-like contacts The interposer module interconnects those contacts, via internal wiring, to contact lands on the main substrate. Engineering changes are accomplished by changing the internal wiring within the interposer module.
A similar interposer module is shown in U.S. Pat. No. 4,803,595 to Kraus et al. In that patent, engineering change pads and discrete wires are avoided by employing an interposer module with X and Y wiring planes. Engineering changes are accomplished by selectively removing via interconnections within the interposer module. Additionally, short jumper metallurgy may be applied between appropriate internal wiring planes and vias to provide additional internal interconnections. Kraus et al. also show the use of a decoupling capacitor mounted on the surface of the interposer structure, adjacent to semiconductor chips supported thereon. The decoupling capacitor is connected to internal wiring in the interposer.
A number of publications describing various interposer structures are found in issues of the IBM Technical Disclosure Bulletin. McMahon, Jr., in Vol. 18, No. 5, Oct. 1975, pages 1440, 1441, shows an interposer structure with correction pads on its uppermost surface to enable engineering changes. In Vol. 24, No. 9, Feb. 1982, pages 4637, 4638, an interposer structure is shown by Ecker et al. which, when combined with engineering change pads on the surface of a common substrate that supports the interposer, enables engineering changes to be made. In Vol. 29, No. 4, Sep. 1986, pages 1694, 1695 a further interposer/engineering change system is described which employs replacement interposers. The interposer of this publication employs unused bump lands on a chip and connects them to engineering change channels buried in a common substrate. X and Y buried engineering change wires within the interposer are employed. In Vol. 26, No. 9, Feb. 1984, pages 4590, 4591, Feinberg et al. show a pair of interposers that support the periphery of a master chip which has a slave chip mounted beneath it and between the interposers. In Vol. 27, No. 8, Jan. 1985, pages 4672, 4673, Harvilchuck et al. describe still another interposer which contains signal redistribution networks that reduce the number of required ceramic layers in the common supporting module. In Vol. 30, No. 4, Sep. 1987 pages 1786, 1787 an interposer chip carrier is described which includes decoupling capacitors interconnected to edges of the module. These capacitors provide for decoupling action within the module.
As is further known, decoupling capacitances are often found necessary in electronic packaging. It is generally desirable to position the decoupling capacitance as close as possible to the semiconductor chip. In U.S. Pat. No. 4,328,530 to Bajorek et al., such coupling capacitances are placed in notches within a substrate in an attempt to locate the capacitance as close as possible to the solder bonds between the chips and the substrate. Stacks of laminated ceramic capacitors are inserted into the slots and serve as power planes. In another patent to Bajorek et al. (U.S. Pat. No. 4,349,862), a chip-carrying module is described wherein decoupling capacitors are placed internal to the module between interconnecting vias. Bajorek (FIG. 2) also shows the use of interposer modules to support semiconductor wafers and locates the decoupling capacitors therein. In U.S. Pat. No. 4,744,007 to Black et al., still another electronic packaging technique including decoupling capacitances is shown. In this instance, the decoupling capacitances are electrically coupled to input/output contacts of the semiconductor chip, with the capacitances being mounted below the chip, as discrete devices.
More powerful and faster computers are possible with more chips and shorter interconnection lengths between chips. It therefore becomes important to reduce the spacings between chips while maintaining the wiring capability of the substrate. An engineering change scheme that uses the surface area of the substrate or reduces the wiring capability of the substrate defeats the optimum package objective. Thus, an interposer engineering change scheme with surface mounted decoupling capacitors or a capacitor interposer with an engineering change scheme that uses wiring in the substrate are less than optimum.
Accordingly, it is an object of this invention to provide a module where integrated circuit chips are mounted in a planar wall-to-wall configuration on a common ceramic substrate.
It is another object of this invention to provide an improved interposer module for supporting semiconductor chips on a common ceramic substrate.
It is still another object of this invention to provide an interposer module having integral decoupling capacitance provided within the module.
It is yet another object of this invention to provide an interposer module having engineering change capability provided by X/Y interconnection lines which may be selectively connected to or disconnected from vias within the module.